Printed circuit board (PCB) routing plays a crucial role in high-speed circuits, but it is often one of the final steps in the circuit design process. There are many aspects to high-speed PCB routing, and extensive literature has been written on the subject. This article mainly explores the routing issues of high-speed circuits from a practical perspective, aiming to help new users pay attention to the various considerations when designing high-speed circuit PCB routing. Another goal is to provide a review for customers who haven't been involved in PCB routing for some time.

Due to space limitations, this article cannot discuss all issues in detail, but we will focus on the key aspects that are most effective in improving circuit performance, shortening design time, and reducing revision time.

Although this discussion primarily targets circuits related to high-speed operational amplifiers, the issues and methods covered here are generally applicable to routing most other high-speed analog circuits. When operational amplifiers operate at very high radio frequency (RF) ranges, circuit performance largely depends on PCB routing. A high-performance circuit design that looks good "on paper" may only deliver mediocre performance if carelessly routed. Considering and paying attention to important details throughout the routing process in advance will help ensure the intended circuit performance.

Schematic

Although an excellent schematic doesn't guarantee good routing, good routing starts with an excellent schematic. Consider carefully when drawing the schematic and pay attention to the overall signal flow of the circuit. If the schematic has a smooth, stable signal flow from left to right, the PCB should ideally have a similarly good signal flow. Provide as much useful information as possible on the schematic. Sometimes when the circuit design engineer is unavailable, clients may ask us to help solve circuit problems, and the designers, technicians, and engineers involved, including us, will greatly appreciate comprehensive schematics.

Besides common reference designators, power ratings, and tolerance information, what other information should be included in the schematic? Here are some suggestions to turn an ordinary schematic into a top-notch one: include waveforms, mechanical information about the enclosure, trace lengths, blank areas; indicate which components need to be placed on the top side of the PCB; provide adjustment information, component value ranges, thermal information, controlled impedance traces, notes, a brief description of circuit operation... (and more).

Trust No One

If you are not designing the routing yourself, always allocate sufficient time to carefully review the routing designer's work. A little prevention here is worth a hundred times the cure. Don't assume the router understands your intentions. Your input and guidance are most critical early in the routing design process. The more information you can provide and the more involved you are throughout the routing process, the better the resulting PCB will be. Set tentative checkpoints for the routing design engineer—perform quick reviews based on the routing progress reports you want. This "closed-loop" approach prevents the routing from going astray, minimizing the likelihood of rework.

Instructions for the routing engineer should include: a brief description of the circuit function, a PCB sketch indicating input and output locations, PCB stack-up information (e.g., board thickness, number of layers, details of each signal layer and ground plane—power, ground, analog signals, digital signals, and RF signals); which signals are needed on each layer; required placement locations for critical components; exact locations for bypass components; which traces are critical; which lines require controlled impedance; which lines require matched lengths; component dimensions; which traces need to be kept away from (or close to) others; which components need to be kept away from (or close to) others; which components must be placed on the top or bottom of the PCB. Never complain about providing too much information to others—too little? Yes; too much? No.

A lesson learned: about ten years ago, I designed a multi-layer surface-mount board with components on both sides. Many screws secured the board inside a gold-plated aluminum enclosure (due to strict shock resistance requirements). Bias feedthrough pins passed through the board. These pins were connected to the PCB via bond wires. It was a complex assembly. Some components on the board were for test setup (SAT). However, I had explicitly specified the location of these components. Can you guess where these components were installed? Correct, on the bottom side of the board. The product engineers and technicians were very unhappy when they had to disassemble the entire unit, perform the setup, and then reassemble it. Since then, I have never made that mistake again.

Placement

Just like in PCB design, placement is everything. Where a circuit is placed on the PCB, where its specific components are installed, and what adjacent circuits are nearby are all extremely important.

Typically, input, output, and power supply locations are predetermined, but the circuitry in between requires "creative freedom." That's why paying attention to routing details yields significant returns. Start with the placement of key components and consider both the specific circuit and the overall PCB. Defining key component locations and signal paths from the outset helps ensure the design meets its intended operational goals. Getting the design right the first time reduces cost and stress—shortening the development cycle.

Bypassing the Power Supply

Bypassing the power supply at the amplifier's power pins to reduce noise is a crucial aspect of PCB design—applicable to both high-speed operational amplifiers and other high-speed circuits. There are two common configurations for bypassing high-speed operational amplifiers.

Power Pin to Ground: This method is generally the most effective in most cases, using multiple parallel capacitors to directly connect the op-amp's power pins to ground. Typically, two parallel capacitors are sufficient—but adding more may benefit certain circuits.

Using capacitors of different values in parallel helps ensure the power pins see very low AC impedance across a broad frequency range. This is particularly important at frequencies where the amplifier's Power Supply Rejection Ratio (PSRR) degrades. These capacitors help compensate for the amplifier's reduced PSRR. Maintaining a low-impedance path to ground over many decades of frequency helps prevent harmful noise from entering the op-amp.

Figure 1 illustrates the advantage of using multiple parallel capacitors. At low frequencies, larger capacitors provide a low-impedance path to ground. But once the frequency reaches their self-resonant frequency, the capacitive nature diminishes, and they gradually become inductive. That's why using multiple capacitors is important: as one capacitor's frequency response starts to roll off, another's begins to take effect, maintaining very low AC impedance across many frequency decades.

Figure 1. Capacitor impedance vs. frequency.

Start directly at the op-amp's power pins; the capacitor with the smallest capacitance value and physical size should be placed on the same side of the PCB as the amplifier—and as close as possible to it. The ground terminal of the capacitor should connect directly to the ground plane using the shortest lead or trace. This ground connection should be as close as possible to the amplifier's load side to minimize interference between the supply and ground. Figure 2 shows this connection method.

Figure 2. Parallel capacitors bypassing power pins to ground.

Repeat this process for the next larger capacitor value. It's best to start by placing a 0.01 µF capacitor (the minimum) and position a 2.2 µF (or slightly larger) low-ESR electrolytic capacitor nearby. A 0.01 µF capacitor in an 0508 package size offers low series inductance and excellent high-frequency performance.

Power Pin to Power Pin: Another configuration uses one or more bypass capacitors connected between the op-amp's positive and negative supply pins. This method is typically used when implementing four capacitors (two per rail to ground) is difficult. Its drawback is that capacitor package sizes may need to be larger because the voltage across the capacitor is twice that of the single-supply bypass method. Higher voltage requires higher device breakdown voltage ratings, increasing package size. However, this method can improve PSRR and distortion performance.

Since each circuit and layout is different, capacitor configuration, quantity, and values must be determined based on the specific circuit requirements.

Parasitic Effects

Parasitic effects are those sneaky elements that infiltrate your PCB and cause elusive, troublesome glitches in the circuit (literally). They are the hidden parasitic capacitances and inductances that creep into high-speed circuits. These include parasitic inductance formed by package leads and excessively long traces; parasitic capacitance formed between pads and ground, pads and power planes, and pads and traces; interactions between vias; and many other possible parasitic effects. Figure 3(a) shows a typical non-inverting op-amp schematic. However, considering parasitic effects, the same circuit might look like Figure 3(b).

Figure 3. Typical operational amplifier circuit: (a) original design, (b) considering parasitic effects.

In high-speed circuits, very small values can affect performance. Sometimes just a few picofarads (pF) of capacitance are enough. Example: If there's only 1 pF of additional parasitic capacitance at the inverting input, it can cause a peak of nearly 2 dB in the frequency domain (see Figure 4). If the parasitic capacitance is large enough, it can cause circuit instability and oscillation.

Figure 4. Additional peaking caused by parasitic capacitance.

When searching for problematic parasitic sources, a few basic formulas for estimating the size of such parasitic capacitances may be useful. Equation (1) calculates the capacitance of parallel plates (see Figure 5).

Equation (1)

Where C is the capacitance, A is the plate area in cm², k is the relative dielectric constant of the PCB material, and d is the distance between plates in cm.

Figure 5. Capacitance between two plates.

Trace inductance is another parasitic effect to consider, caused by excessively long traces or lack of a ground plane. Equation (2) shows the formula for calculating trace inductance (see Figure 6).

Equation (2)

Where W is the trace width, L is the trace length, and H is the trace thickness. All dimensions are in mm.

Figure 6. Trace inductance.

The oscillation in Figure 7 shows the effect of a 2.54 cm trace at the non-inverting input of a high-speed op-amp. Its equivalent parasitic inductance is 29 nH (10⁻⁹ H), enough to cause sustained low-level ringing throughout the transient response period. Figure 7 also shows how using a ground plane can reduce the impact of parasitic inductance.

Figure 7. Pulse response with and without a ground plane.

Vias are another source of parasitics; they can introduce parasitic inductance and capacitance. Equation (3) calculates parasitic inductance (see Figure 8).

Equation (3)

Where T is the PCB thickness, and d is the via diameter in cm.

Figure 8. Via dimensions.

Equation (4) shows how to calculate the parasitic capacitance introduced by a via (see Figure 8).

Equation (4)

Where εᵣ is the relative permittivity of the PCB material. T is the PCB thickness. D1 is the pad diameter surrounding the via. D2 is the clearance hole diameter in the ground plane. All dimensions are in cm. On a 0.157 cm thick PCB, a single via can add 1.2 nH of parasitic inductance and 0.5 pF of parasitic capacitance; this is why constant vigilance is necessary during PCB routing to minimize parasitic effects.

Ground Planes

There is actually far more to discuss than covered here, but we will highlight some key characteristics and encourage readers to further explore this topic.

A ground plane serves as a common reference voltage, provides shielding, aids heat dissipation, and reduces parasitic inductance (though it can increase parasitic capacitance). While using a ground plane has many benefits, implementation must be done carefully, as it imposes certain limitations on what can and cannot be done.

Ideally, one layer of the PCB should be dedicated as a ground plane. The best results are achieved when this entire plane remains uninterrupted. Never borrow areas of this dedicated ground plane for routing other signals. Since the ground plane can cancel magnetic fields between conductors and the plane, it reduces trace inductance. Disrupting an area of the ground plane can introduce unexpected parasitic inductance for traces above or below that area.

Because a ground plane typically has a large surface area and cross-sectional area, it keeps resistance to a minimum. At low frequencies, current chooses the path of least resistance, but at high frequencies, it chooses the path of least impedance.

However, there are exceptions; sometimes a smaller ground plane is better. High-speed op-amps may perform better if the ground plane is removed from under the input or output pads. This is because the ground plane at the input introduces parasitic capacitance, increasing the op-amp's input capacitance, reducing phase margin, and causing instability. As seen in the discussion on parasitic effects, even 1 pF of capacitance at the op-amp input can cause significant peaking. Capacitive loads at the output—including parasitic ones—create poles in the feedback loop. This reduces phase margin and can make the circuit unstable.

If possible, analog and digital circuits—including their respective grounds and ground planes—should be separated. Fast rise times can cause current spikes to flow into the ground plane. The noise generated by these fast current spikes can degrade analog performance. Analog and digital grounds (and power supplies) should be connected at a single common point to minimize circulating digital and analog ground currents and noise.

At high frequencies, a phenomenon called "skin effect" must be considered. Skin effect causes current to flow on the outer surface of a conductor—resulting in a reduced effective cross-sectional area, thus increasing DC resistance. Although skin effect is beyond the scope of this article, here is a good approximation for skin depth (in cm) in copper:

Equation (5)

Using low-resistivity plating metals helps reduce skin effect.

Routing and Shielding

Various analog and digital signals exist on a PCB, ranging from high to low voltage or current, and from DC to GHz frequencies. Ensuring these signals do not interfere with each other is very challenging.

Recalling the advice from the "Trust No One" section, the key is to think ahead and develop a plan for how to handle signals on the PCB. It's important to note which signals are sensitive and determine what measures must be taken to ensure signal integrity. The ground plane provides a common reference point for electrical signals and can also be used for shielding. If signal isolation is needed, the first step should be to provide physical distance between signal traces.

Here are some practical guidelines to follow:

Reducing the length of long parallel runs and the proximity of signal traces on the same PCB can reduce inductive coupling. Reducing the length of adjacent long traces on neighboring layers can prevent capacitive coupling. Signal traces requiring high isolation should run on different layers and—if complete isolation is not possible—should run orthogonally, with a ground plane placed between them. Orthogonal routing minimizes capacitive coupling, and the ground trace acts as an electrical shield. This method can be used when forming controlled impedance traces. High-frequency (RF) signals typically travel on controlled impedance traces. That is, the trace maintains a characteristic impedance, e.g., 50Ω (typical for RF applications). The two most common controlled impedance traces, microstrip⁴ and stripline⁵, achieve similar results but in different ways.

Microstrip controlled impedance traces, as shown in Figure 13, can be used on either side of the PCB; they use the underlying ground plane directly as their reference plane.

Figure 13. Microstrip transmission line.

Equation (6) can be used to calculate the characteristic impedance for an FR4 board.

Equation (6)

Where H is the distance from the ground plane to the signal trace, W is the trace width, T is the trace thickness; all dimensions are in mils (10⁻³ inches). εᵣ is the dielectric constant of the PCB material.

Stripline controlled impedance traces (see Figure 14) use two ground planes, with the signal trace sandwiched between them. This method uses more board area, requires more PCB layers, is sensitive to dielectric thickness variations, and is more expensive—so it is typically used only in demanding applications.

Figure 14. Stripline controlled impedance trace.

The formula for calculating characteristic impedance for stripline is shown in Equation (7).

Equation (7)

Guard rings, or "guard traces," are another common shielding method used with op-amps to prevent parasitic currents from entering sensitive nodes. The principle is simple—completely surround the sensitive node with a guard trace, held or forced (low impedance) to the same potential as the sensitive node, thereby diverting absorbed parasitic currents away from the sensitive node.

Figure 15(a) shows the schematic of guard rings used in inverting and non-inverting op-amp configurations. Figure 15(b) shows typical routing for guard rings in an SOT-23-5 package.

Figure 15. Guard rings. (a) Inverting and non-inverting operation. (b) SOT-23-5 package.

Conclusion

High-quality PCB routing is crucial for successful operational amplifier circuit design, especially for high-speed circuits. A good schematic is the foundation of good routing; close collaboration between the circuit design engineer and the layout engineer is essential, particularly regarding component and trace placement. Considerations include power supply bypassing, minimizing parasitic effects, using ground planes, the impact of op-amp packaging, and routing and shielding methods.

1. During PCB design, bypass/filter capacitors at the chip's power supply should be placed as close as possible to the device, typically within 3 mm.

2. The small ceramic bypass capacitors at the op-amp's power pins can provide energy for the amplifier's high-frequency performance when processing high-frequency input signals. Capacitance selection depends on the input signal frequency and the amplifier's speed. For example, a 400 MHz amplifier might use parallel 0.01 µF and 1 nF capacitors.

3. When purchasing capacitors and other components, also pay attention to their self-resonant frequency. Capacitors around the self-resonant frequency (e.g., 400 MHz) are ineffective.

4. When routing the PCB, avoid running other traces under the amplifier's input/output pins and feedback resistors to minimize parasitic capacitive coupling and improve amplifier stability.

5. Surface-mount devices (SMDs) offer better high-frequency performance and smaller size.

6. Keep traces as short as possible during routing, while also paying attention to their length and width to minimize parasitic effects.

7. For power traces, the worst parasitic characteristics are DC resistance and self-inductance, so widen power traces as much as possible.

8. The currents on amplifier input and output connection traces are very small, making them highly susceptible to interference; parasitic effects can be particularly harmful.

9. For signal paths longer than 1 cm, it's best to use controlled impedance traces terminated at both ends (with matching resistors).

10. To address stability issues when an amplifier drives capacitive loads, a common technique is to introduce a series output resistor (Rout) placed close to the op-amp, providing isolation from the capacitive load.